Appeal No. 98-3047
Application No. 08/576,539
state transition decision unit both reads and writes to the failure state 618 entry, to monitor and update
the status. The decision unit also reads and writes to timer 619, to update and monitor the particular
timer for the corresponding virtual path in order to, for example, update the failure state 618 entry to
“normal,” and notify the host processor, when the timer reflects that an AIS cell has not been received
for three seconds.
Thus, contrary to appellants’ arguments, status determinations are made irrespective of the
order of the received packets. The VP Table-2 contains historical status information. The circuitry
does more than evaluate connections which relate to the current cell or packet as it is received.
We therefore sustain the rejection of Claims 7 and 8 under 35 U.S.C. § 103 over Miyagi.
Claim 9
Appellants contend, on pages 7 and 8 of the Brief, that Miyagi fails to disclose a
“postprocessing circuit” and a “monitoring circuit” as set forth in Claim 9. However, the reference
discloses a “monitoring circuit” that is very much like appellants’ disclosed “monitoring circuit,” and
certainly no different from that claimed. As shown in Fig. 1 of Miyagi, line connection/terminator 101
monitors the physical line and notifies the fault detection circuitry via
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