Appeal No. 2001,0712
Application 08/148,887
scheme for allocating variables to registers and memory, and
this scheme is based on a machine state level model (MSL).
This model is directed to optimizing register storage based on
analyzing read and write operations for register and memory
locations.
It is then pointed out by Appellants that neither
reference teaches or suggests the desirability of using the
teachings of the other to produce Appellants' invention, and
that Hitchcock is not directed to developing a resource
allocation device for a compiler, but for an automated
hardware design tool. Furthermore, there is no teaching
concerning the need or desirability of extracting instruction
sequences to determine an optimized compiler output.
Finally in this regard, Appellants contend that the
reasons to combine as set forth by the Examiner are not 8
directed to the combination of references supporting the
rejection, and fails to consider the effects that the actual
instruction sequences have on performance.
8Final rejection, page 3, last three lines through page 4,
lines 1-5.
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