Appeal No. 1996-3541
Application 08/275,307
Rather than repeat the positions of the appellant and the examiner, reference is
made to all of the various briefs and reply briefs as well as answers and supplemental
answers filed in this appeal.
OPINION
We reverse both art rejections of record and institute two new rejections, one under
the first paragraph of 35 U.S.C. § 112 and another under 35 U.S.C. § 103 interpreting the
Andersen reference in a different manner than the examiner.
Turning first to the rejection of claims 30 through 34 under 35 U.S.C. § 102 as
anticipated by Goodman, each of independent claims 30 and 33 require that a master
microprocessor essentially program a memory by causing instructions to be stored
therein. Master processor 11 in Figure 1 of Goodman is not taught to perform this function
either in the RAM 10 or any other memory element that may be associated with the DMA
controller 12 and/or the slave processor 13. Although the RAM 10 is taught to be either a
dynamic or static RAM, it too is not disclosed to store instructions for any of the processing
devices 11 through 13. Even though the bidirectional bus 14 conveys data bidirectionally
among the devices in Figure 1, none of the data are taught to comprise instruction or
programming-type information. The slave processor 13 contains its own ROM as pointed
out by appellant which, on its own, would not be given to being programmed or
reprogrammed, once it has been initially programmed, by any
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