Appeal No. 1997-3734 Page 2
Application No. 08/329,806
1. A method of semiconductor integrated circuit fabrication comprising:
forming a dielectric upon a substrate;
forming an opening in said dielectric, exposing said substrate;
forming a layer of material chosen from the group consisting of polysilicon and amorphous
silicon within said opening, and overlying all of the exposed portion of said substrate and said dielectric,
said layer not completely filling said opening;
exposing said layer of material to WF , thereby forming a tungsten plug which completely fills
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said opening, and forming a tungsten layer which covers said dielectric;
etching said tungsten layer.
The prior art references of record relied upon by the Examiner in rejecting the appealed claims are:
Shioya et al. (Shioya) 4,906,593 Mar. 06, 1990
Dixit et al. (Dixit) 4,960,732 Oct. 02, 1990
Sun et al. (Sun) 4,994,410 Feb. 19, 1991
Chung et al. (Chung) 5,094,981 Mar. 10, 1992
Manocha et al. (Manocha) 5,141,897 Aug. 25, 1992
Japanese Patent Applications
Fujita 62-243325 Oct. 23, 1987
Shiki (Tadaki) 63-052441 Mar. 05, 19881
Kobayashi et al. (Kobayashi) 2-090518 Mar. 30, 1990
2 Wolf, Silicon Processing for the VLSI Era 240-254 (1990).
1As both the Examiner and the Appellants use "Tadaki" to refer to this reference we will do
likewise.
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