Appeal No. 1997-3734 Page 4
Application No. 08/329,806
USPQ2d 1635, 1637 (Fed. Cir. 1998). “In other words, the examiner must show reasons that the
skilled artisan, confronted with the same problems as the inventor and with no knowledge of the
claimed invention, would select the elements from the cited prior art references for combination in the
manner claimed.” In re Rouffet, 149 F.3d 1350, 1357, 47 USPQ2d 1453, 1458 (Fed.Cir. 1998).
Focusing on claim 1, the only independent claim, we note that this claim requires the formation of a
layer of polysilicon or amorphous silicon overlying all of the exposed portion of the substrate and
dielectric. This layer of silicon material is then exposed to WF to form a tungsten layer which covers
6
said dielectric. It is this tungsten layer covering the dielectric which is etched. In the processes of
Tadaki, Fujita, Kobayashi , and Shioya, the silicon layer is etched back before any step of converting2
silicon to tungsten. None of these references describe etching a tungsten layer much less a tungsten
layer covering the dielectric. To remedy this deficiency, the Examiner looks to the disclosure in Wolf at
page 245 which summarizes two methods for the implementation of vertical vias. In describing one of
these methods, Wolf states the following:
1. Filling of vias through deposition of metal into the opened via to form a plug
in the opening. In theory, this can be accomplished either independently of the metal-
runner formation process, or through simultaneous fabrication of the plugs and metal
runner. An example of the latter is the deposition and patterning of a blanket CVD W
layer.
2In making our determination, we rely on the translations of the Japanese documents which are
of record in the application.
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