Appeal No. 1997-4034
Application No. 08/260,269
review, we will affirm the anticipation rejection of claims 1,
2, and 11 and the obviousness rejections of claims 3 through
9, but reverse the obviousness rejection of claims 10 and 12.
The only limitation argued by appellant for claim 1 is
"read control signal generating means for generating a read
control signal used to read said video signal stored in said
memory means at a time synchronized with said timing signal."
All agree that Yoshioka discloses a timing signal relating to
a driving state of the recording means and a read start signal
synchronized with the timing signal. However, appellant
explains (Brief, page 8) that in Yoshioka's device "the pulse
value of read start pulses RS ... is latched at each pulse
occurrence of read clock pulses CP and the latched value, if
2
a pulse is latched, operates to reset the address in counter
404." Appellant then concludes that "the read address signal
(i.e., the output of counter 404) is synchronized with read
clock pulses CP and not with read start pulses RS." We
2,
disagree.
In Figure 7, Yoshioka shows read start pulses (Fig. 7f)
synchronized with the read address controller output (Fig. 7i)
and also with the tach pulses, or the timing signal relating
4
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007