Appeal No. 1998-3411
Application No. 08/548,113
to have direct access to the peripherals of the other module”. It
is asserted that the expression “the processor of any of the
modules to become temporarily the master etc.” means that each of
a plurality of modules has a respective processor that is capable
of having direct access to the peripherals of another one of the
modules. Appellant contends that both references teach systems
having one single processor capable of accessing the memory of
other processors and, consequently, that neither reference teaches
nor suggests that any of the modules are capable of accessing
another processor’s memory.
We find this argument persuasive and are of the opinion that
the rejection should not be sustained.
In the sentence bridging pages 3 and 4 of the answer, the
examiner acknowledges that “Persaud does not teach any of the
processor modules can access any of the other processor modules
local bus.”
With respect to Bederman, we agree with the examiner’s
position at page 7 of the answer that this reference teaches a
means for sharing a first memory means in alternation between
processors. As noted by the examiner, such language appears in
Bederman in claim 1, specifically at lines 6 and 7. This language
of claim 1 is supported by Figure 1 of Bederman because memory 4
can be shared by master processor 1 and slave processor 6, and
memory 3 can be shared by master processor 1 and processor 5.
3
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