Appeal No. 1999-0007
Application 08/688,218
(b) mapping the physical cell library based on layout design
rules of the second manufacturing process, the layout design
rules of the second manufacturing process defining routing grid
dimensions for the second integrated circuit;
(c) characterizing the physical cell library and producing a
timing library based upon a plurality of device models of the
second manufacturing process;
(d) generating a second plurality of libraries including a
place and route library; the second plurality of libraries
defining characteristics of the second integrated circuit; and
(e) utilizing a place and route database of the first
manufacturing process and the routing grid dimensions of the
first manufacturing process to map into a second place and route
data base of the second manufacturing process; the place and
route database of the second manufacturing process providing
routing grid dimensions in such a manner that the position of the
cell placements and inter-connections are relatively the same as
in the first manufacturing process; the second place and route
database defining the second integrated circuit.
The Examiner relies on the following references:
Upton et al. (Upton) 5,351,197 Sept. 27,
1994
Dai et al. (Dai) 5,452,239 Sept. 19,
1995
Claims 3 through 6, 9 through 13, 18 and 19 stand rejected
under 35 U.S.C. § 103(a) as being unpatentable over Upton in view
of Dai.1
The Examiner notes an objection to the drawings (answer-unnumbered third page), however1
(continued...)
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