Appeal No. 1999-0294
Application No. 08/727,256
correction capabilities of error checking and correction (ECC)
memory controllers.
Representative independent claim 1 is reproduced as
follows:
1. A method of verifying error checking and correction
(“ECC”) capabilities of a memory controller electrically
connected to a processor via a bus, said memory controller
controlling access to a memory device, the method comprising:
disabling said ECC capabilities of said memory
controller;
while said ECC capabilities of said memory controller are
disabled, writing a test pattern and a first ECC code to a
selected location in said memory device, said first ECC code
corresponding to a natural state of said bus and said test
pattern being at least one bit different than a pattern
corresponding to said first ECC code, thereby inducing a
memory error;
subsequent to said writing, enabling said ECC
capabilities of said memory controller;
subsequent to said enabling, reading data stored at said
selected memory location using said memory controller.
The examiner relies on the following references:
Solomon et al. (Solomon) 5,305,326 Apr. 19, 1994
Arroyo et al. (Arroyo) 5,502,732 Mar. 26, 1996
Claims 1-23 stand rejected under 35 U.S.C. 103 as
2–
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