Appeal No. 1999-0294
Application No. 08/727,256
device and data transfers into and out of the memory; and
writes a test pattern and a first ECC code to a selected
location in a memory device, with the test pattern being at
least one bit different than a pattern corresponding to the
first ECC code, thus inducing a memory error.
The examiner recognizes that Arroyo clearly does not show
the features of disabling the ECC capabilities of the memory
controller and does not show the enabling of the ECC
capabilities of the memory controller. Therefore, the
examiner turns to Solomon for the teaching of a user
data/parity matching operation in an I/O control processor
being performed under command of a host computer and the
examiner concludes therefrom that it would have been obvious
to modify the method of Arroyo to include the step of
providing a command to the components of Arroyo’s controller
to control the use of components in the controller. The
examiner’s rationale is that Arroyo suggests that the ECC
logic will be implemented in hardware on the memory
controller, with the hardware having ECC test components being
utilized only during a read operation [Paper No. 4-pages 5-6].
We do not find that the examiner has established a prima
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