Appeal No. 1999-0320
Application No. 08/426,751
available to store the request." The examiner relies on 2
teachings of the reference at column 61, lines 42-50, and also
column 68, lines 50-56. These teachings are that acknowledge
line 20e of Figure 22 is asserted by the bus interface 21 to
the CPU 10 in the cycle after it has received with no parity
errors the write address which was driven by the CPU in a
cycle (column 61), and that if parity is good and the address
is recognized as being in interface chip 21, then acknowledge
line 20e is asserted and the information is moved into holding
registers in queues 339 and 340 (Figure 23) so that the
latches 336 are free to sample the next cycle (column 68).
The portions of Bouchard's disclosure relied on by the
examiner are not a teaching of the claimed subject matter nor
do they suggest that subject matter because they have nothing
to do with acceptance of a request by a device as defined in
the claim and to which the request is directed. With respect
to claim 13, CPU 10 of Bouchard is the processor and bus 11 is
the shared system bus. Memories 12 and 16, and CPUs 28 of the
2In their brief, appellants' arguments are limited to this
element of the claim.
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