Appeal No. 1999-1126 Page 2
Application No. 08/722,486
conventionally have been required to equalize bit lines in an
SRAM, the use of the pulses prolongs access times and degrades
overall performance of the SRAM.
The appellants’ SRAM employs a current mode data path to
overcome the aforementioned shortcomings. More specifically,
their SRAM uses two cascade complementary differential current
amplifiers in a readout circuit. The amplifiers employ
special bias circuits and provide improved amplifier
operation. Advantageously, a small amplifier differential
input resistance reduces the voltage swing of differential
lines thereby eliminating the need for equalization clocks.
The unique bias circuit of the claimed invention improves
operation of the amplifiers and allows the amplifiers to be
used in differential cascaded applications such as in an SRAM
read data path.
Claim 12, which is representative for our purposes,
follows:
12. A semiconductor memory comprising a
plurality of memory cells arranged in rows and
columns at least one two stage differential current
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