Appeal No. 1999-1634
Application 08/729,399
Representative claim 1 is reproduced below:
1. A reference current generating circuit comprising:
a reference voltage generator for generating a predetermined reference voltage;
a resistor ladder circuit connected to said reference voltage generator and having a
predetermined number of taps for outputting a corresponding number of different divided
voltages obtained from a voltage generated by said reference voltage generator;
a control circuit, connected to the predetermined number of taps of said resistor
ladder circuit, for outputting a selected divided voltage of said different divided voltages;
and
a MOS transistor having a gate connected to receive said selected divided voltage
and a source connected to a reference power supply terminal;
wherein a current flowing through a drain of the MOS transistor is extracted as a
predetermined output reference current.
The following references are relied on by the examiner:
Nakamura et al. (Nakamura) 5,459,684 Oct. 17, 1995
McClure et al. (McClure) 5,654,663 Aug. 5, 1997
(effective filing date Dec. 16, 1994)
Claims 1, 7 and 9 stand rejected under 35 U.S.C. § 102(e) as being anticipated by
McClure. Claims 2-4, 6, 8 and 10 stand rejected under 35 U.S.C. §103. As evidence of
obviousness, the examiner relies upon McClure in view of Nakamura.
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