Appeal No.1999-1940
Application No. 08/654,760
self aligned vertical floating gate. The second principal
difference is that the bit line is formed on top of the substrate
and not in the substrate and makes contact with the drain of
every cell at the location of the cell. A further understanding
of the invention can be achieved by the following claim:
1. A nonvolatile memory cell array comprised of a
plurality of EEPROM memory cells, each cell comprising:
a semiconductor substrate;
a vertical MOS transistor formed by alternating N-
type and P-type doped layers in said substrate and
wherein a well is etched into said substrate through
said alternating N-type and P-type layers such that
said alternating layer surround said well, said well
having a floating gate of conductive material formed
therein which is self aligned to not extend laterally
beyond edges of said well and insulated from and
overlying said alternating N-type and P-type layers by
a layer of gate insulating material;
a word line contact comprising a layer of
conductive material formed on said substrate so as to
extend down into said well and overlie said floating
gate but insulated therefrom by an insulation layer;
and
a bit line contact comprising a layer of
conductive material formed on said substrate so as to
be in electrical contact with the drain region of said
vertical MOS transistor formed in said substrate.
The examiner relies on the following reference:
Mori 5,071,782 Dec. 10, 1991
2
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