Appeal No. 1999-2375
Application No. 08/892,822
BACKGROUND
The appellants’ invention relates to a data processor having BIOS packing
compression/decompression architecture. An understanding of the invention can be
derived from a reading of exemplary claims 1 and 6, which are reproduced below.
1. A data processing system capable of an expedited initialization process,
comprising:
a central processing unit (CPU);
a system memory, including system RAM memory, for storing data in the form of
electrical signals;
a first port for receiving an input device generating electrical input signals;
at least one second port for supplying electrical output signals to output devices;
a system bus logically interconnecting the CPU, the system memory and the first
and second ports;
the CPU including a BIOS having BIOS code, an initial portion of the BIOS code for
carrying out prescribed functions being in uncompressed form, including code required to
enable the system memory and including power on self test (POST) code, and a remaining
portion of the BIOS code for carrying out other prescribed functions being in compressed
form, for carrying out prescribed functions including converting operating signals
developed by an operating system executed by the CPU into electrical signals compatible
with devices that are responsive to signals provided by the CPU to the system bus;
means for writing the initial portion of the BIOS code for carrying out the prescribed
functions in uncompressed form and the remaining compressed portion of the BIOS code
for carrying out the other prescribed functions to the system RAM memory; and
means for decompressing selected portions, for carrying out the prescribed
functions, of the compressed BIOS code written to and stored in the system RAM memory
for expediting the initialization process of the data processing system.
2
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