Appeal No. 2000-0260
Application No. 08/675,865
dopant being doped at a substrate depth not less than or greater
than a depth of the phosphorus dopant in the substrate. A gate is
formed on the active area with source and drain regions formed
adjacent to the gate.
Claim 1 is illustrative of the invention and reads as follows:
1. A method of fabricating a field effect transistor comprising
the steps of:
a)doping an area of a substrate with phosphorus and arsenic
dopants, wherein the arsenic dopant is doped at a depth in the
substrate greater than a depth of the phosphorus dopant in the
substrate.
b) forming a gate on the area; and
c) forming source and drain regions adjacent to the gate in
the area.
The Examiner relies on the following prior art:
Lee 5,548,143 Aug. 20, 1996
(effectively filed Apr. 29, 1994)
Claims 1, 3-10, and 12-17 stand rejected under 35 U.S.C.
§ 112, first paragraph, as being based on an inadequate disclosure.
Claims 1, 5, 7, 8, 10, 12, 16, and 17 stand rejected under
35 U.S.C. § 102(e) as being anticipated by Lee. Claims 3, 4, 6, 9,
and 13-15 stand finally rejected under 35 U.S.C. § 103(a) as being
unpatentable over Lee.
2
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