Appeal No. 2000-0414
Application No. 08/811,101
BACKGROUND
The appellants’ invention relates to a video graphics controller with high speed
line draw processor. An understanding of the invention can be derived from a reading
of exemplary claim 1, which is reproduced below.
1. A graphics device comprising:
a first register storing a first value indicative of the coordinates of a
first endpoint of a line;
a second register storing a second value indicative of the
coordinates of a second endpoint of the line;
clock circuitry including a clock signal which includes a plurality of
clock cycles;
a command register for storing control bits;
a line draw engine coupled to receive the clock signal and at least
one control bit from the command register, the line draw engine to
generate line data based on said first and second values, the generation
of line data beginning in the clock cycle immediately succeeding a clock
cycle in which the second value is stored in the second register; and
a datapath circuitry including a graphics device output node for
coupling to a memory, the datapath circuitry including a mask signal input.
The prior art reference of record relied upon by the examiner in rejecting the
appealed claims is:
Miyashita et al. (Miyashita) 5,068,802 Nov. 26, 1991
2
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