Appeal No. 2000-1187 Page 5
Application No. 08/723,174
With respect to claim 1, the appellants argue that Cohen
teaches neither “at least a bus bridge having a slot” nor “at
least a logic gate connected between said bridge and said slot.”
The appellants further point out that Cohen uses programmable
configuration registers within a VLSI chip to report to the host
processor the device ID and the application code of the card
being used (brief, p. 4, reply brief, p. 2).
The examiner responds to the appellants’ arguments by
referring to the last paragraph of the specification that
suggests the use of any other logic gates, boards or driving
signal for device ID select (answer, p. 4). The examiner
concludes that other sources for selecting the target device such
as Cohen’s activating a control bit after the “retry mode” is de-
activated, anticipates the claims (answer, pp. 4 & 5).
A rejection for anticipation under section 102 requires that
each and every limitation of the claimed invention be disclosed
in a single prior art reference. In re Paulsen, 30 F.3d 1475,
1478-79, 31 USPQ2d 1671, 1673 (Fed. Cir. 1994), citing In re
Spada, 911 F.2d 705, 708, 15 USPQ2d 1655, 1657 (Fed. Cir. 1990).
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