Appeal No. 2000-1187 Page 7
Application No. 08/723,174
remedy the deficiencies of Cohen in a rejection based on
anticipation. Accordingly, we reverse the rejection of claims 1,
6, 11, 16 and 17 under 35 U.S.C. § 102 over Cohen.
Turning to the rejection of claims 5, 10 and 15, the
appellants argue that Cohen lacks any teachings related to a bus
bridge driving 32 address data lines and using one of the 32
address data lines reserved to select local buses for enabling
the device. The appellants further point out that the reference
fails to anticipate the claims since it does not discuss the
subject of address data lines (brief, p. 4).
The examiner, in response, points to col. 2, lines 51-59 of
Cohen for teaching the activation of selected control lines on
the PCI bus by the PCI interface chip in response to accesses to
its registers from the system processor (answer, p. 6). The
examiner further refers to the [PCI] control [signal] lines
between PCI bus 10 and PCI state machine and combinatorial logic
means 31 (Fig. 4) as the address line.
Cohen in col. 6, lines 35 through 43 states:
Still referring to Fig. 4, a set of the data lines (on
the PCI bus) called the PCI data bus 10A interconnects the
PCI configuration registers to PCI bus 10. a control
architectured line called the PCI-RST#LINE interconnects the
PCI access grant register 24 to the PCI bus 10. Finally, a
set of PCI control signal lines necessary to activate the
so-called retry function of the PCI bus, interconnects the
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