Appeal No. 2001-0297
Application No. 09/196,375
the application. Accordingly, even though we completely agree with the examiner’s
analysis, we cannot sustain the rejection based upon a lack of written description.
35 U.S.C. § 103
Appellant argues that the result of the combined structure of claim 3 is to allow
transistors designed for both high BVceo and high ft to be formed on the same monolithic
integrated circuit and in a cost efficient manner without added steps. (See brief at page
4.) Appellant argues that no such structure is taught by Maeda, Akcasu or combination
thereof. (See brief at page 4.) Appellant argues that the solution to the problem
recognized by the present invention is not taught or suggested. (See brief at page 4.)
We disagree with appellant that the combination of Maeda and Akcasu must teach or
suggest the same solution that appellant has achieved. Rather, we find the examiner’s
stated motivation to increase the packing density to be convincing. (See answer at
page 6.) Additionally, the examiner maintains that the language of claim 3 does not
require transistors designed for both high BVceo and high ft to be formed on the same
monolithic integrated circuit and in a cost efficient manner without added steps. (See
answer at page 6.) We agree with the examiner.
With this said, it is the examiner’s initial burden to establish a prima facie case
of obviousness. While we agree with the examiner that the references are properly
combinable, we find no motivation to limit the teachings of Akcasu to one of the two
transistors taught by Maeda. In our view, Akcasu teaches the use of varied thickness
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