Appeal No. 2001-1571
Application No. 09/062,002
BACKGROUND
The invention relates to a method and system for accessing a cache memory
within a data processing system. Representative claim 1 is reproduced below.
1. A method for accessing a cache memory within a data processing system
utilizing an effective address, wherein said effective address includes a byte
field, a line field, and an effective page number field, wherein said cache memory
includes a memory array along with a directory and a translation lookaside
buffer, said method comprising the steps of:
providing a translation array that includes an identical number of rows as
in said translation lookaside buffer, and an identical number of array entries
within each row as the product of cache lines per page of a system memory and
an associativity of said cache memory; and
in response to a cache access by an effective address, determining
whether or not said cache memory stores data associated with said effective
address utilizing said translation array.
The examiner relies on the following references:
Brenza 4,797,814 Jan. 10, 1989
Martens et al. (Martens) 5,970,512 Oct. 19, 1999
(filed Mar. 27, 1997)
Claims 1-10 stand rejected under 35 U.S.C. § 103 as being unpatentable over
Martens and Brenza.
We refer to the Final Rejection (Paper No. 6) and the Examiner's Answer (Paper
No. 13) for a statement of the examiner's position1 and to the Brief (Paper No. 11) and
1 The Answer refers to the rejection set forth in the non-final action, “Paper No. 4.” However, the
rejection was repeated and made final in Paper No. 6.
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