Appeal No. 2001-2444
Application No. 09/419,176
1. A method of inlaid interconnect fabrication,
comprising the steps of:
(a) provide a dielectric layer;
(b) form a silicon carbide layer on said
dielectric layer;
(c) form vias and trenches in said silicon
carbide and dielectric layers;
(d) deposit conducting material on said silicon
carbide and dielectric; and
(e) planarize to remove said conducting material
outside of said vias and trenches with said silicon
carbide as a planarization stop.
THE REFERENCES
Fiordalice et al. (Fiordalice) 5,578,523 Nov. 26, 1996
Chiang et al. (Chiang) 5,817,572 Oct. 06, 1998
THE REJECTION
Claims 1 and 2 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Fiordalice in view of Chiang.
OPINION
We reverse the aforementioned rejection. We need to address
only claim 1, which is the sole independent claim.
Fiordalice discloses a method of inlaid interconnect
fabrication comprising providing, in order, a conductive
2
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