Appeal No. 1999-1286
Application No. 08/567,950
The claims
Claims 1, 5, and 17 are representative:
1. A method for physically marking, on a silicon wafer, a surface of an
integrated circuit deemed to be defective during a testing step so as to
modify a visual appearance of the surface, the method comprising steps
of:
identifying a defective integrated circuit; and
marking the defective integrated circuit at a plurality of locations by
exposing the surface of the defective integrated circuit to laser radiation of
sufficient magnitude such that the defective integrated circuit will not
operate.
5. The method according to claim 1, wherein the laser radiation is
focused in such a way that a marking diameter at one of the plurality of
locations is different than a marking diameter at at least one other of the
plurality of locations.
17. A method of inspecting a plurality of integrated circuits on a silicon
wafer, the method comprising steps of:
testing the plurality of integrated circuits;
identifying defective integrated circuits; and
exposing a surface of each of the defective integrated circuits to
laser radiation of sufficient magnitude such that the defective integrated
circuit will not operate, the step of exposing including a step of creating a
mark on the surface of each of the defective integrated circuits at a
plurality of locations.
The prior art
The examiner has relied on the following prior art in support of the rejections:
Abe3, Japanese patent publication 63-237,431, published October 3, 1988.
Shils et al. (Shils), U.S. Patent No. 4,510,673, issued April 16, 1985.
3 A USPTO translation is of record, a copy of which accompanies this decision.
- 3 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: November 3, 2007