Appeal No. 1999-1449
Application 08/640,351
specification, page 1, lines 14-18. The sampled amplitude read
channel includes a sampling device (24) that asynchronously
samples the analog read signal to generate discrete time sample
values (Xk) (25). See figure 3, and specification, page 14,
lines 4-5. The sampled amplitude read channel further includes
an adaptive equalizer (B103), responsive to the discrete time
sample values (Xk) (25) for generating equalized sample values
(32) according to a target response. See specification, page 14,
lines 4-9. The sampled amplitude read channel also includes an
interpolated timing recovery circuit (B100) for generating
interpolated sample values (B102). See figure 3 and
specification, page 20, lines 1-3. Additionally, the sampled
amplitude read channel includes a discrete time sequence detector
(34) for detecting the digital data from the interpolated sample
values (B102).
Figure 4B is a detailed block diagram of the interpolated
timing recovery circuit (B100) shown in figure 3. See
Specification, page 11, lines 11-13, and page 19, lines 14-15.
Figure 8B is a detailed block diagram of the adaptive equalizer
(B103) shown in figure 3. See Specification, page 11, lines
22-23, and page 35, lines 17-18. Figure 8C is an alternative
embodiment of the detailed block diagram of the adaptive
2
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Next
Last modified: November 3, 2007