Appeal No. 1999-1449
Application 08/640,351
Panduit Corp. v. Dennison Mfg., 810 F.2d 1561, 1567-68, 1 USPQ2d
1593, 1597 (Fed. Cir. 1987), Cert denied, 481 U.S. 1052 (1987).
We note that claim 1 reads as follows:
the adaptive equalizer comprises an interpolation circuit,
responsive to the interpolated sample values, for
generating the error value ek synchronous with the discrete
time sample values.
On page 35, line 17 through page 36, line 18, Appellants’
specification discloses that the sample values, X(k), are
provided to the adaptive equalizer B103 shown in figure 8B of the
sample rate of the A/D (24). Figure 8B shows that the adaptive
equalizer B103 includes an FIR filter C100 and an interpolator
circuit B122. In particular, Appellants’ specification states
that:
Because the FIR filter C100 operates on the sample values
prior to the interpolated timing recovery loop B100, its
order can be increased over the prior art without adversely
affecting the latency of timing recovery (i.e., the number
of filter coefficients can be increased).
The output Yk 32 of the FIR filter C100 is input into
the interpolator B122 for generating the interpolated sample
values Yk+t B102. The interpolated sample values Yk +t B102
are input into a slicer B141 (FIG 4B) which generates
estimated sample values ~Yk +t. The estimated sample values
~Yk +t are subtracted from the interpolated sample values Yk +t
at adder C102 to generate a sample error value ek +t C104
that is synchronized to the baud rate rather than the sample
rate. Because the LMS algorithm operates on sample values
Xk at the sample rate, it is necessary to convert the error
value ek +t C104 into an error value ek C112 synchronous to
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