Appeal No. 1999-1888
Application No. 08/473,504
read operation associated with an instruction is performed prior
to the instruction arriving at the functional unit which forms
the execute stage of the instruction processing pipeline, thereby
reducing the number of clock cycles required by the functional
unit. Claim 1 is illustrative of the claimed invention, and it
reads as follows:
1. A method for predicting a data address which will be
referenced by a plurality of instructions residing in a basic
block when said basic block is fetched, comprising:
generating a data prediction address;
fetching data associated with said data prediction address
from a data cache into a data buffer; and
accessing said data buffer for load data from a decode stage
of an instruction processing pipeline.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Eickemeyer (Eickemeyer I) 5,313,634 May 17, 1994
Eickemeyer et al. (Eickemeyer II) 5,377,336 Dec. 27, 1994
Kusano 5,412,786 May 02, 1995
Claims 1 through 3 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Eickemeyer II.
Claims 5 through 14 and 16 stand rejected under 35 U.S.C.
§ 103 as being unpatentable over Eickemeyer II in view of
Eickemeyer I.
Claims 17 through 25 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Eickemeyer I in view of Eickemeyer II.
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