Appeal No. 1999-1888
Application No. 08/473,504
Claim 26 stands rejected under 35 U.S.C. § 103 as being
unpatentable over Eickemeyer I in view of Kusano.
Reference is made to the Examiner's Answer (Paper No. 16,
mailed February 1, 1999) for the examiner's complete reasoning in
support of the rejections, and to appellant's Brief (Paper No.
15, filed November 16, 1998) and Reply Brief (Paper No. 17, filed
April 5, 1999) for appellant's arguments thereagainst.
OPINION
We have carefully considered the claims, the applied prior
art references, and the respective positions articulated by
appellant and the examiner. As a consequence of our review, we
will reverse the obviousness rejections of claims 1 through 3, 5
through 14, and 16 through 26.
Independent claim 1 recites accessing a data buffer "from a
decode stage of an instruction processing pipeline." The
examiner admits (Answer, page 4) that Eickemeyer II fails to
"explicitly state" this claimed limitation, but asserts that it
would have been obvious "since Eickemeyer shows that the load
data is available in the decode stage," and "because doing so
would have eliminated the normal data fetch cycle from the
execution unit pipeline."
Appellant (Brief, pages 5-6) explains that Figure 2 of
Eickemeyer II shows that the decode unit accesses history buffer
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