Ex Parte MILLS et al - Page 2



          Appeal No. 1999-2614                                                        
          Application No. 08/667,826                                                  

               The claimed invention relates to a graphics controller                 
          circuit which includes a register file with a plurality of                  
          registers.  Commands addressed to virtual registers are accepted            
          by the graphics controller, and a plurality of instructions are             
          generated including instructions to access one of the registers             
          in the register file.  According to Appellants (specification,              
          page 6), by having commands which are directed to virtual                   
          registers and generating multiple instructions in response                  
          thereto, the graphics controller permits an access command to be            
          combined into one command on the system bus, thereby minimizing             
          the amount of data transferred over the system bus.                         
               Claim 1 is illustrative of the invention and reads as                  
          follows:                                                                    
                    1.  A graphics controller circuit for use in a computer           
               system, the computer system comprising a bus and a host, the           
               host being coupled to the bus, comprising:                             
                    a host interface for receiving a single command on the            
               bus from the host, and generating a plurality of                       
               instructions in response to the command, at least one of the           
               plurality of instructions comprising a set register                    
               instruction, and at least another of the plurality of                  
               instructions being an execute instruction; and                         
                    an execution circuit, coupled to the host interface,              
               for executing the plurality of instructions to execute the             
               command.                                                               


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