Appeal No. 2001-0416
Application No. 09/074,292
Background
The performance of semiconductor devices is related to
several factors, one of which is the width of the polysilicon
gates of FET transistors formed on the device. Specification,
page 1, lines 22-24. According to appellant, prior art attempts
to reduce the final gate, as well as other feature dimensions
have shown limited success. Id. at lines 25-29. In particular,
while these methods may reduce the main feature width, the
overall spacing of the feature increases such that the pitch of
the device does not decrease and there is no gain in density.
Id. at lines 29-31. Appellant claims to have achieved a high
performance semiconductor device by a manufacturing method which
produces a semiconductor device with features having a dimension
of ½ the minimum pitch determined by the parameters of the
manufacturing process. Id., page 2, lines 24-27.
Discussion
1. Rejection of claims 1 and 2 under 35 U.S.C. § 112,
second paragraph
According to the examiner, the claim 1 limitation “½ the
minimum pitch” is subjective and indefinite. In particular, the
examiner maintains that this term is indefinite in that the
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