Appeal No. 2001-0482
Application No. 09/186,078
Rho et al. (Rho)1 5,904,541 May 18, 1999
(filed Jun. 20, 1997)
Wristers et al. (Wristers) 5,930,620 Jul. 27, 1999
(filed Sep. 12, 1997)
Liaw et al. (Liaw) 5,960,276 Sep. 28,1999
(filed Sep. 28,1998)
Stanley Wolf et al. (Wolf), Silicon Processing for the VLSI Era, 212 (Lattice Press, 1986).
Claims 1-35 stand finally rejected under 35 U.S.C. § 103(a). As evidence of obviousness,
the Examiner offers Son in view of Fulford with respect to claims 1-3, 5-9, 11, and 16-19. To this
basic combination, Liaw is separately added with respect to claims 4, 10, 12, and 13, and Wolf is
separately added with respect to claim 14. Further, the combination of Son, Fulford, Wristers, and
Liaw is applied against claims 15, 20, and 21. In the rejection against claims 22-24, 26-30, and 35,
the Examiner relies on the combination of Rho in view of Gardner. To the Rho and Gardner
combination, the Examiner separately adds Liaw with respect to claims 25 and 31-34.
Rather than reiterate the arguments of Appellants and the Examiner, reference is made to the
Briefs2 and Answer for their respective details.
1 Although used in the Examiner’s prior art rejection, the Rho reference is not listed in the cited prior art at
page 3 of the Answer.
2 The Appeal Brief was filed October 3, 2000 (Paper No. 12). In response to the Examiner’s Answer dated
December 20, 2000 (Paper No. 13), a Reply Brief was filed February 20, 2001 (Paper No. 14), which was
acknowledged and entered by the Examiner as indicated in the communication dated March 30, 2001 (Paper No.
16).
3
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