Appeal No. 2001-1093
Application No. 09/252,186
The disclosed invention relates to the use of a metal
silicide liner on metal features and vias of a semiconductor
device.
Claim 1 is illustrative of the claimed invention, and it
reads as follows:
1. A semiconductor device comprising:
a substrate having active regions; and
an interconnection system comprising:
a first patterned metal layer, comprising metal
features, over the substrate;
a plurality of patterned metal layers, each patterned
metal layer containing metal features, above the first patterned
metal layer terminating with an uppermost patterned metal layer;
vias electrically connecting metal features of
different patterned metal layers;
contacts electrically connecting active regions to metal
features of the first patterned metal layer;
air gaps between the patterned metal layers, metal features,
and vias; and
a metal silicide liner on the metal features and vias,
wherein the air gaps are substantially continuous throughout the
interconnection system.
2
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