Appeal No. 2001-1421
Application No. 09/128,226
forming a plurality of bumps on the pads, wherein the bumps
have a first height and an air space is naturally formed between
sides of the bumps and the passivation layer;
coating a first underfill material layer over the first
semiconductor substrate at least filling the air space, wherein a
thickness of the first underfill material layer is less than the
first height of the bumps;
performing a die sawing process on the first semiconductor
substrate to from [sic, form] a plurality of dies; and
performing a flip-chip process on each of the dies to adhere
each of the dies to a second substrate.
The Examiner relies on the following prior art:
Goossen 5,975,408 Nov. 02, 1999
(filed Oct. 23, 1997)
Charles A. Harper (Harper), “Electronic Packaging and
Interconnection Handbook,” (Second Edition, McGraw-Hill, New
York) 5.52-5.53 and 10.29-10.34 (1997).
Claims 1-15 stand finally rejected under 35 U.S.C. § 103(a)
as being unpatentable over Goossen in view of Harper.
Rather than reiterate the arguments of Appellants and the
Examiner, reference is made to the Briefs1 and Answer for their
respective details.
1 The Appeal Brief was filed September 11, 2000 (Paper No. 9). In
response to the Examiner’s Answer dated October 24, 2000 (Paper No. 10), a
Reply Brief was filed December 26, 2000 (Paper No. 11), which was acknowledged
and entered by the Examiner as indicated in the communication dated January
18, 2001 (Paper No. 12).
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