Appeal No. 2001-2097
Application No. 09/052,849
input clock waveforms using combinations of integer and non-
integer divisions of the input clocks. Included in the clock
divider circuit are a first portion for performing integral
division of the input clock waveforms in combination with a
second portion for phase slip control which performs non-integer
division of the source input waveforms.
Claim 1 is illustrative of the invention and reads as
follows:
1. A clock divider circuit comprising:
an integral divider portion for dividing a source input
clock signal by an integral divisor to produce a divided clock
signal; and
a phase slip portion for applying a predetermined phase slip
to said divided clock signal to produce a phase slipped divided
clock signal as a non-integral division of said source input
clock signal.
As the sole rejection by the Examiner before us, claims 1-20
stand finally rejected under 35 U.S.C. § 112, first paragraph, as
being based on an inadequate disclosure.
Rather than reiterate the arguments of Appellants and the
Examiner, reference is made to the Brief (Paper No. 14) and
Answer (Paper No. 15) for their respective details.
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