Appeal No. 2001-2097
Application No. 09/052,849
specifically indicated how Appellants’ disclosure would not be
enabling with regard to the particular clock divider circuitry
recited in the appealed claims. For example, the Examiner has
never indicated what is deficient in Appellants’ disclosure
related to the integral divider portions and phase slip portions
of the claimed circuit structure. Our review of Appellants’
disclosure, beginning at page 3, reveals a detailed description
of the operation of the claimed clock divider circuit as well as
a detailed gate level (Figures 3-6) description of the structure
of the previously mentioned integral divider and phase slip
portions. We are further persuaded by Appellants’ argument
(Brief, page 9) that clear evidence of the enabling nature of
their disclosure is the inclusion in the original disclosure of a
complete listing of the actual implementation of the claimed
invention in the Verilog HDL language, which, as evidence on the
record would indicate, is a hardware description language widely
used by circuit design engineers.
In view of the above, we find that the Examiner has not
established a reasonable basis for challenging the sufficiency of
the instant disclosure. Accordingly, we will not sustain the
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