Appeal No. 2001-2125
Application No. 08/906,537
selected one of the “round” bits introduced by the Booth encoding
is processed at an otherwise unused input terminal of the
accumulator without affecting the overall result of the
multiplier/accumulator operation. According to Appellants
(specification, page 12), the removal of the selected “round” bit
from the partial product adders of the multiplier permits an
elimination of a full adder stage from the multiplier.
Claim 1 is illustrative of the invention and reads as follows:
1. A method for cooperatively combining a computer-implemented
multiplier and an accumulator established to receive an output of
said multiplier comprising the steps of:
causing an input term of said multiplier to be coded according
to an algorithm for reducing a number of partial products generated
by operation of said multiplier;
configuring adder stages of said multiplier for summing said
partial products so that all partial product bits except for at
least one round bit are processed in a set of adders comprising
said adder stages;
causing said at least one round bit to be processed by said
accumulator; and
causing an output of said multiplier to be provided as an
input to said accumulator.
2
Page: Previous 1 2 3 4 5 6 7 8 9 10 Next
Last modified: November 3, 2007