Ex Parte FARROKH et al - Page 6




          Appeal No. 2001-2125                                                        
          Application No. 08/906,537                                                  


               In response to the obviousness rejection, Appellants assert            
          several arguments in support of their contention that the Examiner          
          has failed to establish a prima facie case of obviousness.  In              
          particular, Appellants assert (Brief, pages 8-10) that no clear             
          motivation for combining Taborn with De Angel has been provided by          
          the Examiner, and, even if combined, the ensuing structure would            
          not result in the particular combination as claimed.                        
               After reviewing the arguments of record from both Appellants           
          and the Examiner, we are in general agreement with Appellants’              
          position as stated in the Brief.  In particular, our interpretation         
          of the disclosure of De Angel coincides with that of Appellants,            
          i.e., the adder stage 30, which the Examiner asserts is adding              
          “round bits” A1-A7, is merely an end-stage adder for the multiplier         
          itself.  Given this disclosure of De Angel, it is not apparent as           
          to how and in what manner Taborn would be modified to produce the           
          structure as claimed in which “round bits” are provided as inputs           
          to the accumulator part of the multiply/accumulator cooperative             
          combination.                                                                
               We recognize that the Examiner, in the “Response to Argument”          
          portion of the Answer at page 6, suggests the well-known aspects of         
          modifying a multiplier to form a multiplier/accumulator by                  
          introducing a 3-2 carry save adder between a multiplier array and a         
                                          6                                           





Page:  Previous  1  2  3  4  5  6  7  8  9  10  Next 

Last modified: November 3, 2007