Appeal No. 2001-2212
Application No. 09/019,409
established on a silicon substrate. Plural stacks are formed on
the at least one tunnel oxide layer with each stack including a
first polysilicon layer. After forming an interpoly dielectric
layer on at least some of the stacks, a second polysilicon layer is
deposited on at least a portion of the interpoly dielectric layer
to establish memory cell control gates. After the establishment of
the control gates, isolation trenches are formed in the substrate.
Claim 1 is illustrative of the invention and reads as follows:
1. A process for making a flash memory core having source and
drain regions, comprising the step of:
providing at least one silicon substrate;
establishing at least one tunnel oxide layer on the substrate;
establishing plurals stacks on the tunnel oxide layer, each
stack including a first polysilicon layer;
implanting channel stop dopant in the silicon substrate;
depositing a field oxide material on at least portions of the
silicon substrate over the channel stop dopant;
forming at least one interpoly dielectric layer on at least
some of the stacks;
depositing at least one second polysilicon layer on at least a
portion of the interpoly dielectric layer, such that plural memory
cell control gates are established; and
after the step of establishing plural memory cell control
gates, establishing isolation trenches in the substrate.
2
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