Appeal No. 2001-2459
Application No. 09/277,281
section connected to said pin associated with said
respective pad, said pull-up device having a P-channel MOS
transistor with a gate and connected between said connection
node and a high potential, said gate receiving a voltage for
controlling said P-channel MOS transistor, said pull-up
device having a further P-channel MOS transistor with a
further gate and connected between said connection node and
the high potential, said further gate receiving a low
potential.
The following reference is relied on by the Examiner:
Intrater 5,818,251 Oct. 6, 1998
(filed Jun. 11, 1996)
Claims 1, 4-7 and 10-12 stand rejected under 35 U.S.C.
§ 102(e) as being anticipated by Intrater.
Rather than reiterate the viewpoints of the Examiner and
Appellants, we make reference to the answer (Paper No. 15, mailed
April 18, 2001) for the Examiner’s complete reasoning and the
brief (Paper No. 14, filed February 26, 2001) for Appellants’
arguments thereagainst.
OPINION
Appellants argue that Intrater cannot anticipate the claimed
subject matter as the reference is merely directed to applying a
high voltage and a low voltage to each conductive trace in order
to test for a proper connection (brief, page 12). Appellants
further state that the circuit connections of Intrater are
directly tested whereas the claimed subject matter relates to
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