Appeal No. 2001-2459
Application No. 09/277,281
measuring the output performance of a circuit and what Intrater
describes as “functional tester” (id.). Additionally, Appellants
assert that the reference teaches neither a pull-up device
holding the pad at a high potential, nor two MOS transistors
receiving high and low potentials respectively (id.).
In response to Appellants’ arguments, the Examiner relies on
Figure 1 of Intrater and points out that the claimed pull-up
device is shown as the MOS FET transistor 46 whereas the second
MOS transistor is disclosed as the NPN Bipolar Junction
Transistor (BJT) MOS 30 (answer, page 6). Additionally, the
Examiner asserts that the gate of the MOSFET transistor 46
“receives a voltage (VTEST) for controlling the P-channel” and a
second MOS transistor pull-down device is provided with a
“holding current (VLOAD)” (id.).
A rejection for anticipation under section 102 requires that
each and every limitation of the claimed invention be disclosed
in a single prior art reference. See Atlas Powder Co. v. Ireco
Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999);
In re Paulsen, 30 F.3d 1475, 1478-79, 31 USPQ2d 1671, 1673 (Fed.
Cir. 1994). Anticipation is established only when a single prior
art reference discloses, expressly or under the principles of
inherency, each and every element of a claimed invention as well
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