Appeal No. 2002-0094 Page 2
Application No. 09/346,435
Claims 9, 12-23, 25, and 26 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Hause2 in view of Bothra3 (Answer at pp. 3-5)4. Appellant states that the
claims stand or fall separately. We will consider the claims separately in so far as they are
argued separately in accordance with 37 CFR § 1.192(c)(8)(2001). We have jurisdiction over the
appeal under 35 U.S.C. § 134.
THE CLAIMED SUBJECT MATTER
Claims 9, 15, and 20 are illustrative of the subject matter on appeal:
9. A method of forming an electronic device comprising the steps of:
forming a patterned dielectric layer comprising a material having a low dielectric constant
less than 4.2;
forming an electrical conduction [sic: electrically conductive] sheath layer disposed
adjacent to and over the patterned dielectric layer for electrically diverting etchant particles used
in a plasma etch process away from the dielectric layer;
forming an electrically conductive interconnect layer by a plasma etch process, said
2U.S. Patent 6,013,574 issued to Hause et al. on January 11, 2000. Hause is available as prior art against
the claims as of its effective filing date of January 30, 1996. 35 U.S.C. § 102(e)(2)(2001).
3U.S. Patent 5,981,378 issued to Bothra on November 9, 1999. Bothra is available as prior art against the
claims as of its filing date of July 25, 1997. 35 U.S.C. § 102(e)(2)(2001).
4Wolf et al., 1 Silicon Processing for the VLSI Era 542-47 (1986) was relied upon as evidence of
obviousness, but was not listed in the statement of rejection. We will confine our review to the combination of
Hause and Bothra as it was improper to omit Wolf from the statement of rejection. “Where a reference is relied on
to support a rejection ... there would appear to be no excuse for not positively including the reference in the
statement of rejection.” In re Hoch, 428 F.2d 1341, 1342 n.3, 166 USPQ 406, 407 n.3 (CCPA 1970).
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