Appeal No. 2002-0140
Application No. 09/435,864
number of transistors in the circuit” (brief-page 5). We are
unsure of the point appellants are making. If the clock signals
control the transistors and the skew effect of the transistors
control the output, it seems clear that the clock signals control
the output.
In any event, we suspect appellants are not considering the
breadth of the claims at issue. For example, all that is
required by claim 1 is that both a first and second clock signal
be received by the first stage (clearly, stage 11 in Wu receives
both a clock signal phase 34 and a clock signal phase 3) and that
an output of the first stage is controlled using both the first
and second clock signals (since both clock signals are input in
the first stage in Wu and the output is dependent on those clock
signals, it is clear that the first stage is controlled by the
clock signals). Accordingly, Wu is seen to anticipate the
subject matter claim 1, as well as claim 2.
It is noted that nowhere do appellants argue or deny that Wu
is directed to a method for dealing with an unspecified underlap
requirement in timing-sensitive dynamic circuits of a multi-
clocked system, as claimed. The problem of “clock-skew race,”
described by Wu, appears to be the same problem to which the
instant claimed subject matter is directed.
-5–
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 Next
Last modified: November 3, 2007