Appeal No. 2002-0140
Application No. 09/435,864
Accordingly, we will sustain the rejection of claims 1 and 2
under 35 U.S.C. § 102(b).
We turn, now to the rejection of claims 3, 4 and 6.
Claim 3 requires “triggering a rising edge of the output
using a rising edge of the first clock signal” and claim 4
requires “triggering a falling edge of the output using a rising
edge of the second clock signal.”
The examiner’s answer refers to Figure 7 of Wu for these
limitations and, Figure 7 being an electrical schematic diagram
of a logic structure with no waveforms shown, appellants
understandably argue that it is “not clear” how the reference to
Figure 7 in Wu indicates using a rising edge of the second clock
signal to trigger a falling edge of the output or stabilizing the
output.
We, too, have a bit of trouble discerning how Figure 7 of Wu
indicates the claimed limitations. However, reference to Figure
3, a timing diagram for the circuitry of Figure 1, makes it a bit
clearer.
If we focus on clock signals phase 3 (second clock signal)
and 34 (first clock signal) and output V3, the diagram in Figure
3 clearly shows a rising edge of the output V3 (near the arrow
-6–
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