Appeal No. 2002-0156 Page 2
Application No. 09/300,757
1. An integrated circuit comprising: a phase-frequency detector (PFD) including
two clock input ports, an up signal port and a down signal port;
said PFD comprising digital circuitry including transistors coupled in a
configuration to adjust an amount of overlap of an up output signal pulse and a down
output signal pulse based, at least in part, upon the magnitude of an amount of phase
delay between two respective clock signal pulses applied to the two input ports.
The examiner relies on the following reference:
Noguchi 5,592,110 Jan. 7 1997
Claims 1-3 stand rejected under 35 U.S.C. §102 (e) as anticipated by Noguchi.
Reference is made to the briefs and answer for the respective positions of
appellant and the examiner.
OPINION
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