Appeal No. 2002-0156 Page 3
Application No. 09/300,757
The examiner indicates that Noguchi anticipates the instant claimed invention
because Figures 1 and 2 of Noguchi show a phase comparator (100) used in a phase
locked loop comprising two clock input ports for receiving clock signals (1 and 2) and
two output ports for providing up and down signal pulses, the phase comparator
comprising digital circuitry (figure 1 inherently includes transistors) coupled in a
configuration to adjust the amount of overlap of up and down output signal pulses
based, at least in part, upon the magnitude of an amount of phase delay between two
respective clock signal pulses (figures 2A-2B, 2F-2G) where the overlapping portion of
the up and down signals (figures 2F and 2G) varies accordingly to the phase
differences of the two received clock signals (1 and 2) as called for in claim 1 (see
answer-page 3).
It is appellant’s view that the illustration in Figures 2F and 2G of Noguchi shows
that the pulse width of the first output signal does not change regardless of the phase
delay between the two applied signals, the input signal and the reference signal.
Rather, according to appellant, Noguchi teaches the first and second output signal to
rise and fall based on the input signal, inverted signal, or the narrow width pulse,
referring to column 2, line 63 through column 3, line 5. Appellant points out that the
second output signal in Noguchi has a greater pulse width than the first output signal
and that if the phase delay between the input signal and the reference signal were
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