Appeal No. 2002-0376
Application No. 09/072,137
Appellants’ invention relates to an integrated circuit device, arrangement/wiring
method thereof, arrangement/wiring apparatus thereof, and recoding medium. The
invention uses a compaction process which operates to reduce the minimum chip area
necessary to accommodate the components and routing lines of the device. The
compaction process uses a standard density value to determine when the compaction
process is complete. An understanding of the invention can be derived from a reading
of exemplary claim 1, which is reproduced below.
1. An arrangement/wiring method of an integrated circuit device for
arranging cells each containing at least one element and wiring signal
lines which connect the cells in the integrated circuit device, said
arrangement/wiring method comprising the steps of:
performing a compaction process so as to reduce a chip area of
said integrated circuit device in which the cells have been arranged and
the signal lines have been wired while fulfilling design rules;
obtaining a standard value of element density which is previously
stored in a storage means and indicates a number of elements per unit
area, and comparing said standard value with said element density of said
integrated circuit device to which the compaction process has been
executed; and
repeating the compaction process when said element density is
smaller than said standard value, and terminating the compaction process
when said element density is larger than said standard value.
The prior art of record relied upon by the examiner in rejecting the appealed
claims is as follows:
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