Appeal No. 2002-1305 Page 2
Application No. 09/327,966
Verification via a simulation model is aided by the availability of hardware
description languages such as Verilog and VHDL. These languages describe hardware
at higher levels of abstraction than gates or transistors. (Id. at 2.) According to the
appellants, however, these languages do not include features for testing the "temporal
coverage" of the DUT, (id. at 4), i.e., the behavior of selected variables defining the
DUT over time. Temporal coverage differs from automatic coverage, which is triggered
by the appearance of a line of code or other static event, in that temporal coverage is
driven by the occurrence of events in time. (Id. at 5.)
Accordingly, the appellants' invention tests the quality of a simulation model for a
DUT through temporal coverage of the testing/verification process. Triggering events
are determined according to fixed, predefined sampling times or according to
occurrences of a temporal pattern of state transitions. Temporal data are collected
during the process and analyzed to discern the behavior of selected variables and the
quality of the simulation model for the DUT. More specifically, the data are searched
for a "coverage hole," suggested by the absence of a particular value from a family of
values. (Id. at 5-6.)
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