Ex Parte HOLLANDER et al - Page 6




                 Appeal No. 2002-1305                                                                                  Page 6                     
                 Application No. 09/327,966                                                                                                       


                         "Having construed the claim limitations at issue, we now compare the claims to                                           
                 the prior art to determine if the prior art anticipates those claims."  In re Cruciferous                                        
                 Sprout Litig., 301 F.3d 1343, 1349, 64 USPQ2d 1202, 1206 (Fed. Cir. 2002).  "A claim                                             
                 is anticipated only if each and every element as set forth in the claim is found, either                                         
                 expressly or inherently described, in a single prior art reference."  Verdegaal Bros., Inc.                                      
                 v. Union Oil Co., 814 F.2d 628, 631, 2 USPQ2d 1051, 1053 (Fed. Cir. 1987) (citing                                                
                 Structural Rubber Prods. Co. v. Park Rubber Co., 749 F.2d 707, 715, 223 USPQ 1264,                                               
                 1270 (Fed. Cir. 1984); Connell v. Sears, Roebuck & Co., 722 F.2d 1542, 1548, 220                                                 
                 USPQ 193, 198 (Fed. Cir. 1983); Kalman v. Kimberly-Clark Corp., 713 F.2d 760, 771,                                               
                 218 USPQ 781, 789 (Fed. Cir. 1983)).                                                                                             


                         Here, Shupe discloses "a 'two-pass' simulation algorithm employed by logic                                               
                 simulator 48 to apply the test program 46 to the circuit description 34 and execute the                                          
                 single-level fault simulation."  Col. 12, ll. 39-42.  "This [circuit] description 34 includes                                    
                 identification of the circuit elements and how they are interconnected."  Col. 11, ll. 66-                                       
                 68.  For its part, the "test program 46 compris[es] a set of test vectors or patterns to be                                      
                 applied to the primary inputs of circuit 36."  Id. at ll. 7-9.  "At the start of the logic                                       
                 simulation, the simulator 48 converts the test patterns in the program 46 into 'events'                                          
                 and schedules the events into a time wheel.  The time wheel is divided into slots                                                
                 representing time steps. . . ."  Id. at ll. 54-58.                                                                               








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