Appeal No. 2002-1578
Application No. 08/814,928
programming operation to a specific location, the system processor
has an opportunity to request that a data modification operation to
another memory location be performed while the programming
operation is suspended.
Representative claim 31 is reproduced as follows:
31. A memory device, comprising:
a memory array;
a register to store at least one bit indicating a suspend
status of a write operation for the memory array; and
a control circuit coupled to said memory array and said
register, said control circuit to update said register and to
control an output of a status signal representing said suspend
status of said write operation, and wherein said control circuit
includes:
a first state machine to receive commands for accessing said
memory array or said register, and
a second state machine coupled to said first state machine and
to execute the commands received by said first state machine.
The Examiner relies on the following prior art references:1
Terada et al. (Terada) 5,561,628 Oct. 01, 1996
Leak et al. (Leak) 5,937,424 Aug. 10, 1999
(filed Feb. 27, 1997)
Claims 31-37, all of the appealed claims, stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Appellants’ admitted
1 In addition, the Examiner relies on Appellants’ admissions as to the
prior art at pages 1-3 of Appellants’ specification.
2
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