Appeal No. 2002-1578
Application No. 08/814,928
With respect to representative independent claim 31, the
Examiner (Answer, pages 7-9) proposes to modify the semiconductor
memory device disclosure of Leak. According to the Examiner (id.,
at 8), Leak, which discloses the advantages of suspending both
erase and write operations while performing a read operation to
increase system performance, discloses the claimed invention except
for an explicit description of a status register with a bit
indicator to represent a suspend state. To address this
deficiency, the Examiner turns to Terada which describes a status
register with a bit indicator such as an “ESS” bit to indicate that
an erase operation has been suspended. In the Examiner’s analysis
(id., at 8 and 9), the skilled artisan would have recognized and
appreciated the obviousness of modeling the status register of Leak
after that of Terada to provide a bit indication of suspend status
especially in view of the fact that Leak provides a clear teaching
of outputting status data in response to a read operation.
After reviewing the Examiner’s analysis (Answer, pages 4-6),
it is our view that such analysis carefully points out the
teachings of the Leak and Terada references, reasonably indicates
the perceived differences between this prior art and the claimed
invention, and provides reasons as to how and why the prior art
teachings would have been modified and/or combined to arrive at the
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