Ex Parte NISHIYAMA et al - Page 7



                    Appeal No. 2002-2151                                                                                                                                  
                    Application No. 09/342,234                                                                                                                            

                    lost."  The examiner rationalizes that the structure of                                                                                               
                    controllers in the art almost always contain a microprocessor                                                                                         
                    with an attached RAM to store the information that the processor                                                                                      
                    is working on (final rejection, page 3).                                                                                                              

                    After having reviewed both Weiss and Iihoshi, we must agree                                                                                           
                    with appellants arguments in their brief and reply brief that                                                                                         
                    there is no teaching or suggestion in either Weiss or Iihoshi,                                                                                        
                    whether considered individually or collectively, of a vehicle                                                                                         
                    network system having one master apparatus and a plurality of                                                                                         
                    slave apparatuses connected to a common transmission path,                                                                                            
                    wherein each of the slave apparatuses includes a memory which                                                                                         
                    stores a current apparatus state of the respective slave                                                                                              
                    apparatuses, a determining device for determining whether the                                                                                         
                    current apparatus state stored in the memory of the slave                                                                                             
                    apparatus coincides with the system state in the system state                                                                                         
                    command received from the master apparatus, and an apparatus                                                                                          
                    state changing device for making the current apparatus state                                                                                          
                    stored in the memory of the slave apparatus coincident with the                                                                                       
                    system state command when the determining device determines that                                                                                      
                    the current apparatus state of the slave apparatus does not                                                                                           
                    coincide with the system state in the system state command.                                                                                           
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